--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
--package my_package is
--constant m: natural := 163;
--constant logm: natural := 8;
--end my_package;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_package.all;
entity data_path_divider is
port (
g, h: in std_logic_vector (m-1 downto 0);
clk, ce_abcd, first_step, swap: in std_logic; 
z: out std_logic_vector (m-1 downto 0);
a_0: out std_logic
);
end data_path_divider;

architecture rtl of data_path_divider is
signal b, bb, next_b: std_logic_vector(m downto 0);
signal a, c, d, aa, cc, dd, next_a, next_c, next_d: std_logic_vector(m-1 downto 0);
constant f: std_logic_vector(m downto 0) :=
x"800000000000000000000000000000000000000C9";
constant initial_d: std_logic_vector(m-1 downto 0) := (others => '0');
begin
aa(m-1) <= a(0) and b(m);
iterative_step_a: for j in 161 downto 0 generate
aa(j) <= 
--(not(a(0)) and a(j+1)) or (a(0) and (a(j+1) xor b(j+1)));
a(j+1) xor (a(0) and b(j+1));
end generate;
with first_step select next_a <= h when '1', aa when others;
cc(m-1) <= 
--(not(a(0)) and c(0)) or (a(0) and (c(0) xor d(0)));
c(0) xor (a(0) and d(0));
iterative_step_c: for j in 161 downto 7 generate
cc(j) <= 
--(not(a(0)) and c(j+1)) or (a(0) and (c(j+1) xor d(j+1)));
c(j+1) xor (a(0) and d(j+1));
end generate;
cc(6) <= 
--cc(m-1) xor ((not(a(0)) and c(7)) or (a(0) and (c(7) xor d(7))));
cc(m-1) xor c(7) xor (a(0) and d(7));
cc(5) <= 
--cc(m-1) xor ((not(a(0)) and c(6)) or (a(0) and (c(6) xor d(6))));
cc(m-1) xor c(6) xor (a(0) and d(6));
cc(4) <= 
--(not(a(0)) and c(5)) or (a(0) and (c(5) xor d(5)));
c(5) xor (a(0) and d(5));
cc(3) <= 
--(not(a(0)) and c(4)) or (a(0) and (c(4) xor d(4)));
c(4) xor (a(0) and d(4));
cc(2) <= 
--cc(m-1) xor ((not(a(0)) and c(3)) or (a(0) and (c(3) xor d(3))));
cc(m-1) xor c(3) xor (a(0) and d(3));
cc(1) <= 
--(not(a(0)) and c(2)) or (a(0) and (c(2) xor d(2)));
c(2) xor (a(0) and d(2));
cc(0) <= 
--(not(a(0)) and c(1)) or (a(0) and (c(1) xor d(1)));
c(1) xor (a(0) and d(1));
with first_step select next_c <= g when '1', cc when others;
with first_step select next_b <= f when '1', bb when others;
with swap select bb <= b when '0', '0'&a when others;
with swap select dd <= d when '0', c when others;
with first_step select next_d <= initial_d when '1', dd when others;
registers: process(clk)
begin
if clk'event and clk = '1' then
if ce_abcd = '1' then a <= next_a; b <= next_b; c <= next_c; d <= next_d; 
end if;
end if;
end process registers;
with a(0) select z <= d when '0', c when others;
a_0 <= a(0);
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_package.all;
entity divider_163_7_6_3 is
port(
g, h: in std_logic_vector(m-1 downto 0);
clk, reset, start: in std_logic;
z: out std_logic_vector(m-1 downto 0);
done: out std_logic
);
end divider_163_7_6_3;

architecture circuit of divider_163_7_6_3 is
component data_path_divider is
port(
g, h: in std_logic_vector (m-1 downto 0);
clk, ce_abcd, first_step, swap: in std_logic; 
z: out std_logic_vector (m-1 downto 0);
a_0: out std_logic
);
end component;
subtype states is natural range 0 to 3;
signal current_state: states;
signal ce_abcd, first_step, swap, a_0: std_logic;
subtype small_integers is integer range -m to m-1;
signal dif, min: small_integers;
begin
main_component: data_path_divider port map(g, h, clk, ce_abcd, first_step, swap, z, a_0);
counters: process(clk, current_state)
begin
if clk'event and clk = '1' then
if current_state = 2 then dif <= -1; min <= m-1;
elsif current_state = 3 then
   if a_0 = '0' then
      if dif <= 0 then min <= min-1; end if;
      dif <= dif -1;
   elsif dif >= 0 then
      if dif = 0 then min <= min-1; end if;
      dif <= dif -1;
   else dif <= -dif - 1;
   end if;
end if;
end if;
end process counters;
control_unit: process(clk, reset, current_state)
begin
case current_state is
when 0 to 1 => ce_abcd <= '0'; first_step <= '0'; swap <= '0'; done <= '1';
when 2 => ce_abcd <= '1'; first_step <= '1'; swap <= '0'; done <= '0';
when 3 => 
if min = 0 then ce_abcd <= '0'; else ce_abcd <= '1'; end if; 
first_step <= '0'; 
if a_0 = '1' and dif < 0 then swap <= '1'; else swap <= '0'; end if;
done <= '0';
end case;
if reset = '1' then current_state <= 0;
elsif clk'event and clk = '1' then
case current_state is
when 0 => if start = '0' then current_state <= current_state + 1; end if;
when 1 => if start = '1' then current_state <= current_state + 1; end if;
when 2 => current_state <= current_state + 1;
when 3 => if min = 0 then current_state <= 0; end if;
end case;
end if;
end process;
end circuit;