--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.std_logic_unsigned.all;
--package my_package is
--constant m: natural := 163;
--constant logm: natural := 8;
--end my_package;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_package.all;
entity data_path_multiplier is
port (
a, b: in std_logic_vector (m-1 downto 0);
clk, ce_c, clear_c, load_a, shift_a: in std_logic; 
c: inout std_logic_vector (m-1 downto 0);
equal_zero: out std_logic
);
end data_path_multiplier;

architecture rtl of data_path_multiplier is
signal next_c, int_a: std_logic_vector(m-1 downto 0);
signal count: std_logic_vector(logm-1 downto 0);
begin
iterative_step: for j in 162 downto 8 generate
next_c(j) <= (int_a(m-1) and b(j)) xor c(j-1);
end generate;
next_c(7) <= ((int_a(m-1) and b(7)) xor c(6)) xor c(162);
next_c(6) <= ((int_a(m-1) and b(6)) xor c(5)) xor c(162);
next_c(5) <= (int_a(m-1) and b(5)) xor c(4);
next_c(4) <= (int_a(m-1) and b(4)) xor c(3);
next_c(3) <= ((int_a(m-1) and b(3)) xor c(2)) xor c(162);
next_c(2) <= (int_a(m-1) and b(2)) xor c(1);
next_c(1) <= (int_a(m-1) and b(1)) xor c(0);
next_c(0) <= (int_a(m-1) and b(0)) xor c(162);
shift_register: process(clk)
begin
if clk'event and clk = '1' then
if load_a = '1' then int_a <= a;
elsif shift_a = '1' then
for j in m-1 downto 1 loop int_a(j) <= int_a(j-1); end loop;
int_a(0) <= '0';
end if;
end if;
end process shift_register;
counter: process(clk)
begin
if clk'event and clk = '1' then
if load_a = '1' then count <= conv_std_logic_vector(m-1, logm);
elsif shift_a = '1' then count <= count-1; 
end if;
end if;
end process counter;
with count select equal_zero <= '1' when "00000000", '0' when others;
register_c: process(clk)
begin
if clk'event and clk = '1' then
if clear_c = '1' then c <= (others => '0');
elsif ce_c = '1' then c <= next_c;
end if;
end if;
end process register_c;
end rtl;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_package.all;
entity multiplier_163_7_6_3 is
port (
a, b: in std_logic_vector(m-1 downto 0);
clk, reset, start: in std_logic;
c: inout std_logic_vector(m-1 downto 0);
done: out std_logic
);
end multiplier_163_7_6_3;

architecture circuit of multiplier_163_7_6_3 is

component data_path_multiplier is
port (
a, b: in std_logic_vector (m-1 downto 0);
clk, ce_c, clear_c, load_a, shift_a: in std_logic;
c: inout std_logic_vector (m-1 downto 0);
equal_zero: out std_logic
);
end component;

signal ce_c, clear_c, load_a, shift_a, equal_zero: std_logic;

subtype states is natural range 0 to 3;
signal current_state: states;

begin

main_component: data_path_multiplier port map(a, b, clk, ce_c, clear_c, load_a, shift_a, c, equal_zero);

control_unit: process(clk, reset, current_state, equal_zero)
begin
case current_state is
when 0 to 1 => ce_c <= '0'; clear_c <= '0'; load_a <= '0'; shift_a <= '0'; done <= '1';
when 2 => ce_c <= '0'; clear_c <= '1'; load_a <= '1'; shift_a <= '0'; done <= '0';
when 3 => ce_c <= '1'; clear_c <= '0'; load_a <= '0'; shift_a <= '1'; done <= '0';
end case;
if reset = '1' then current_state <= 0;
elsif clk'event and clk = '1' then
case current_state is
when 0 => if start = '0' then current_state <= current_state + 1; end if;
when 1 => if start = '1' then current_state <= current_state + 1; end if;
when 2 => current_state <= current_state + 1;
when 3 => if equal_zero = '1' then current_state <= 0; end if;
end case;
end if;
end process;

end circuit;