------------------------------------- -- Define data width -- ------------------------------------- package mypackage is constant NBITS :natural := 7; constant MBITS :natural := 9; end mypackage; --------------------------------------------------------- -- Booth-1 multiplier -- ---------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.mypackage.all; entity booth_1 is port ( X: in STD_LOGIC_VECTOR (NBITS-1 downto 0); Y: in STD_LOGIC_VECTOR (MBITS-1 downto 0); P: out STD_LOGIC_VECTOR (NBITS+MBITS-1 downto 0) ); end booth_1; architecture simple_arch of booth_1 is component booth_1_cell Port ( P : in std_logic_vector(MBITS-1 downto 0); Y : in std_logic_vector(MBITS-1 downto 0); x_i : in std_logic_vector(1 downto 0); S : out std_logic_vector(MBITS downto 0) ); end component; type conections is array (0 to NBITS) of STD_LOGIC_VECTOR (MBITS downto 0); Signal wires: conections; Signal eX: STD_LOGIC_VECTOR (NBITS downto 0); begin eX(NBITS downto 1) <= X; eX(0) <= '0'; wires(0) <= (others => '0'); iterac: for I in 0 to NBITS-1 generate mult: booth_1_cell port map (P => wires(i)(MBITS downto 1), Y => Y, x_i => eX(i+1 downto i), S => wires(i+1) ); p(i) <= wires(i+1)(0); end generate; p(MBITS+NBITS-1 downto NBITS) <= wires(NBITS)(MBITS downto 1); end simple_arch; ---------------------------------------------------------- -- booth-1 cell: basic cell for booth 1 multiplier -- ---------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.mypackage.all; entity booth_1_cell is Port ( P : in std_logic_vector(MBITS-1 downto 0); Y : in std_logic_vector(MBITS-1 downto 0); x_i : in std_logic_vector(1 downto 0); S : out std_logic_vector(MBITS downto 0) ); end booth_1_cell; architecture Behavioral of booth_1_cell is signal sS : std_logic_vector(MBITS-1 downto 0); begin the_mux: process(x_i,P, Y) begin case x_i is when "00" => S <= (P(MBITS-1) & P); when "01" => S <= (P(MBITS-1) & P) + (Y(MBITS-1) & Y); when "10" => S <= (P(MBITS-1) & P) - (Y(MBITS-1) & Y); when "11" => S <= (P(MBITS-1) & P); when others => NULL; end case; end process; end Behavioral; ---------------------------------------------------------------------- -- VHDL Test Bench for booth-1 multiplier -- -- Notes: ---------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_signed.all; USE work.mypackage.all; LIBRARY ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY test_exhaustive IS END test_exhaustive; ARCHITECTURE behavioural OF test_exhaustive IS constant DELAY: time := 100 ns; FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt"; COMPONENT booth_1 PORT( X : IN std_logic_vector(NBITS-1 downto 0); Y : IN std_logic_vector(MBITS-1 downto 0); P : OUT std_logic_vector(MBITS+NBITS-1 downto 0) ); END COMPONENT; SIGNAL x : std_logic_vector(NBITS-1 downto 0); SIGNAL y : std_logic_vector(MBITS-1 downto 0); SIGNAL p : std_logic_vector(MBITS+NBITS-1 downto 0); BEGIN uut: booth_1 PORT MAP(X => x, Y => y, P => p); tb_test : PROCESS VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); VARIABLE iP : integer; BEGIN for I in -2**(NBITS-1) to 2**(NBITS-1)-1 loop for J in -2**(MBITS-1) to 2**(MBITS-1)-1 loop x <= CONV_STD_LOGIC_VECTOR (I, NBITS); y <= CONV_STD_LOGIC_VECTOR (J, MBITS); WAIT FOR DELAY/2; ip := CONV_INTEGER(P); IF ( I*J /= iP) THEN write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X); write(TX_LOC,string'(" Y=")); write(TX_LOC, Y); write(TX_LOC,string'(" P=")); write(TX_LOC, P); write(TX_LOC,string'(" (")); write(TX_LOC, i); write(TX_LOC,string'("*")); write(TX_LOC, j); write(TX_LOC,string'("/=")); write(TX_LOC, iP); write(TX_LOC, string'(") ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; writeline(results, TX_LOC); Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; END IF; WAIT FOR DELAY/2; end loop; end loop; ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; END PROCESS; END;