------------------------------------- -- Define data width -- ------------------------------------- package mypackage is constant NBITS :natural := 7; constant MBITS :natural := 8; end mypackage; --------------------------------------------------------- -- Booth-3 multiplier -- ---------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use work.mypackage.all; entity booth_3 is port ( X: in STD_LOGIC_VECTOR (NBITS-1 downto 0); Y: in STD_LOGIC_VECTOR (MBITS-1 downto 0); P: out STD_LOGIC_VECTOR (NBITS+MBITS-1 downto 0) ); end booth_3; architecture simple_arch of booth_3 is component booth_3_cell Port ( P : in std_logic_vector(MBITS-1 downto 0); Y : in std_logic_vector(MBITS-1 downto 0); x_i : in std_logic_vector(3 downto 0); Z : out std_logic_vector(2 downto 0); P_n : out std_logic_vector(MBITS-1 downto 0) ); end component; type conections is array (0 to (NBITS+2)/3+1) of STD_LOGIC_VECTOR (MBITS-1 downto 0); Signal wires: conections; Signal eX: STD_LOGIC_VECTOR (NBITS+2 downto 0); constant bitsCalc : integer := (3-(NBITS mod 3)) mod 3; begin eX <= X(NBITS-1) & X(NBITS-1) & X & '0'; wires(0) <= (others => '0'); iter: for I in 0 to (NBITS+2)/3-1 generate mult: booth_3_cell port map (P => wires(i), Y => Y, x_i => eX(3*i+3 downto 3*i), Z => p(3*i+2 downto 3*i), P_n => wires(i+1) ); end generate; p(MBITS+NBITS-1 downto NBITS+bitsCalc) <= wires((NBITS+2)/3)(MBITS-bitsCalc-1 downto 0); end simple_arch; ---------------------------------------------------------- -- booth-3 cell: basic cell for booth-3 multiplier -- ---------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.mypackage.all; entity booth_3_cell is Port ( P : in std_logic_vector(MBITS-1 downto 0); Y : in std_logic_vector(MBITS-1 downto 0); x_i : in std_logic_vector(3 downto 0); Z : out std_logic_vector(2 downto 0); P_n : out std_logic_vector(MBITS-1 downto 0) ); end booth_3_cell; architecture Behavioral of booth_3_cell is signal S,Long_P, Long_Y, Long_Y_2 , Long_Y_3, Long_Y_4: std_logic_vector(MBITS+2 downto 0); begin Long_P <= P(MBITS-1) & P(MBITS-1) & P(MBITS-1) & P; Long_Y <= Y(MBITS-1) & Y(MBITS-1) & Y(MBITS-1) & Y; Long_Y_2 <= Y(MBITS-1) & Y(MBITS-1) & Y & '0'; Long_Y_3 <= Long_Y + Long_Y_2; Long_Y_4 <= Y(MBITS-1) & Y & "00"; the_mux: process(x_i,Long_P, Long_Y, Long_Y_2, Long_Y_3, Long_Y_4) begin case x_i is when "0000" => S <= Long_P; when "0001" => S <= Long_P + Long_Y; when "0010" => S <= Long_P + Long_Y; when "0011" => S <= Long_P + Long_Y_2; when "0100" => S <= Long_P + Long_Y_2; when "0101" => S <= Long_P + Long_Y_3; when "0110" => S <= Long_P + Long_Y_3; when "0111" => S <= Long_P + Long_Y_4; when "1000" => S <= Long_P - Long_Y_4; when "1001" => S <= Long_P - Long_Y_3; when "1010" => S <= Long_P - Long_Y_3; when "1011" => S <= Long_P - Long_Y_2; when "1100" => S <= Long_P - Long_Y_2; when "1101" => S <= Long_P - Long_Y; when "1110" => S <= Long_P - Long_Y; when "1111" => S <= Long_P; when others => NULL; end case; end process; P_n <= S(MBITS+2 downto 3); Z <= S(2 downto 0); end Behavioral; ---------------------------------------------------------------------- -- VHDL Test Bench for booth-3 multiplier -- -- Notes: ---------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_signed.all; USE work.mypackage.all; LIBRARY ieee; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY test_exhaustive IS END test_exhaustive; ARCHITECTURE behavioural OF test_exhaustive IS constant DELAY: time := 100 ns; FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt"; COMPONENT booth_3 PORT( X : IN std_logic_vector(NBITS-1 downto 0); Y : IN std_logic_vector(MBITS-1 downto 0); P : OUT std_logic_vector(MBITS+NBITS-1 downto 0) ); END COMPONENT; SIGNAL x : std_logic_vector(NBITS-1 downto 0); SIGNAL y : std_logic_vector(MBITS-1 downto 0); SIGNAL p : std_logic_vector(MBITS+NBITS-1 downto 0); BEGIN uut: booth_3 PORT MAP(X => x, Y => y, P => p); tb_test : PROCESS VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); VARIABLE iP : integer; BEGIN for I in -2**(NBITS-1) to 2**(NBITS-1)-1 loop for J in -2**(MBITS-1) to 2**(MBITS-1)-1 loop x <= CONV_STD_LOGIC_VECTOR (I, NBITS); y <= CONV_STD_LOGIC_VECTOR (J, MBITS); WAIT FOR DELAY/2; ip := CONV_INTEGER(P); IF ( I*J /= iP) THEN write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X); write(TX_LOC,string'(" Y=")); write(TX_LOC, Y); write(TX_LOC,string'(" P=")); write(TX_LOC, P); write(TX_LOC,string'(" (")); write(TX_LOC, i); write(TX_LOC,string'("*")); write(TX_LOC, j); write(TX_LOC,string'("/=")); write(TX_LOC, iP); write(TX_LOC, string'(") ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; writeline(results, TX_LOC); Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; END IF; WAIT FOR DELAY/2; end loop; end loop; ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; END PROCESS; END;