-------------------------------------
-- Define data width
--
-------------------------------------
package mypackage is
	constant NBITS :natural := 16;
	constant MBITS :natural := 16;
end mypackage;

---------------------------------------------------------
-- Basic base 2 multiplier (unsigned operands) 
-- 
----------------------------------------------------------		
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;

entity basic_base2_mult is
    port (
        X: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        Y: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
 		  P: out STD_LOGIC_VECTOR (NBITS+MBITS-1 downto 0)
     );
end basic_base2_mult;

architecture simple_arch of basic_base2_mult is

component mult_by_1_bit is
    port (
        A: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
        B: in STD_LOGIC_VECTOR (MBITS-1 downto 0);
        x_i: in STD_LOGIC;
	     S: out STD_LOGIC_VECTOR (MBITS downto 0)
     );
end component;

type conections is array (0 to NBITS) of STD_LOGIC_VECTOR (MBITS downto 0);
Signal wires: conections;

begin
  wires(0) <= (others => '0');
  iterac: for I in 0 to NBITS-1 generate
  mult: mult_by_1_bit port map (A => wires(i)(MBITS downto 1),
  			                        B => Y, x_i => X(i), S => wires(i+1) );
	     p(i) <= wires(i+1)(0);
 end generate;

 p(MBITS+NBITS-1 downto NBITS) <= wires(NBITS)(MBITS downto 1);

end simple_arch;

----------------------------------------------------------
-- mult_by_1_bit. Calculate S <= A+(x_i*B)
--
----------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.mypackage.all;

entity mult_by_1_bit is
    Port ( A : in std_logic_vector(MBITS-1 downto 0);
           B : in std_logic_vector(MBITS-1 downto 0);
           x_i : in std_logic;
			  S : out std_logic_vector(MBITS  downto 0)
          );
end mult_by_1_bit;


architecture Behavioral of mult_by_1_bit is
begin
add_mux: process(x_i,A ,B)
			begin
				if x_i = '1' then
					S <= ('0' & A) + B;
				else
					S <= ('0' & A);
			end if;
end process;

end Behavioral;

----------------------------------------------------------------------
-- VHDL Test Bench for basic_base2_mult
--
-- Notes: 
----------------------------------------------------------------------
LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.mypackage.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_exhaustive IS
END test_exhaustive;

ARCHITECTURE behavioural OF test_exhaustive IS 
constant DELAY: time := 100 ns;
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

	COMPONENT basic_base2_mult
	PORT(
		X : IN std_logic_vector(NBITS-1 downto 0);
		Y : IN std_logic_vector(MBITS-1 downto 0);
		P : OUT std_logic_vector(MBITS+NBITS-1 downto 0)
		);
	END COMPONENT;

	SIGNAL x :  std_logic_vector(NBITS-1 downto 0);
	SIGNAL y :  std_logic_vector(MBITS-1 downto 0);
	SIGNAL p :  std_logic_vector(MBITS+NBITS-1 downto 0);

BEGIN

	uut: basic_base2_mult PORT MAP(X => x, Y => y, P => p);

   tb_test : PROCESS
	VARIABLE TX_LOC : LINE;
	VARIABLE TX_STR : String(1 to 4096);
   BEGIN
		for I in 0 to 2**NBITS-1 loop
			for J in 0 to 2**MBITS-1 loop
				x <= CONV_STD_LOGIC_VECTOR (I, NBITS);
				y <= CONV_STD_LOGIC_VECTOR (J, MBITS);
				WAIT FOR DELAY/2;
				IF ( I*J /= CONV_INTEGER(P)) THEN 
					write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X);
					write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
					write(TX_LOC,string'(" P=")); write(TX_LOC, P);
					write(TX_LOC, string'(" "));
					TX_STR(TX_LOC.all'range) := TX_LOC.all;
					writeline(results, TX_LOC);
					Deallocate(TX_LOC);
					ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				END IF;
				WAIT FOR DELAY/2;
    		end loop;
   	end loop;
		ASSERT (FALSE) REPORT
		"Simulation successful (not a failure).  No problems detected. "
		SEVERITY FAILURE;
   END PROCESS;

END;