-------------------------------------
-- Define Data Width
-------------------------------------
package mypackage is
  constant NBITS: natural := 9;
  constant LOG_P: natural := 4;	
  constant PBITS: natural := 2**LOG_P;	
end mypackage;
---------------------------------------------------------------
-- Goldschmidt Divider 
-- X is 0.xxxxxxxx, Y is 0.xxxxxxxx, and X < Y
---------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE work.mypackage.all;

entity goldschmidt is
port (
	X: in std_logic_vector (NBITS-1 downto 0);	
	Y: in std_logic_vector (NBITS-1 downto 0);	
	Q: out std_logic_vector (PBITS-1 downto 0)	
);
end goldschmidt;

architecture behavioural of goldschmidt is

component goldschmidt_step 
generic(XBITS : integer);
port (
    r: in std_logic_vector (PBITS-1 downto 0);
    d: in std_logic_vector (PBITS-1 downto 0);
    r_n: out std_logic_vector (PBITS-1 downto 0);
    d_n: out std_logic_vector (PBITS-1 downto 0)
);
end component;

type remainder is array (0 to LOG_P+1) of std_logic_vector (PBITS-1 downto 0);
signal r, d: remainder;

begin
r(0)(PBITS-1 downto PBITS-NBITS) <= X; r(0)(PBITS-NBITS-1 downto 0) <= (others => '0'); 
d(0)(PBITS-1 downto PBITS-NBITS) <= Y; d(0)(PBITS-NBITS-1 downto 0) <= (others => '0');
gen_p: for i in 0 to LOG_P-1 generate
	cell: goldschmidt_step 
			generic map(2**(i+1))
		   port map (r => r(i), d => d(i), r_n => r(i+1), d_n => d(i+1) );
end generate;
	celln: goldschmidt_step 
			generic map(PBITS)
		   port map (r => r(LOG_P), d => d(LOG_P), r_n => r(LOG_P+1), d_n => d(LOG_P+1) );
Q <= r(LOG_P+1)(PBITS-1 downto 0);
end behavioural;

---------------------------------------------------------------
-- Goldschmidt Divivider STEP
-- XBITS determines the significant bit calculated
-- 
---------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;

entity goldschmidt_step is
generic(XBITS : integer := 4);
port (
    r: in std_logic_vector (PBITS-1 downto 0);
    d: in std_logic_vector (PBITS-1 downto 0);
    r_n: out std_logic_vector (PBITS-1 downto 0);
    d_n: out std_logic_vector (PBITS-1 downto 0)
);
end goldschmidt_step;

architecture behavioural of goldschmidt_step is

signal d_neg: std_logic_vector (XBITS downto 0);
signal d_neg_long: std_logic_vector (PBITS downto 0);
signal r_n_long, d_n_long: std_logic_vector (PBITS+XBITS downto 0);

begin
  d_neg_long <= not ('0' & d);
  d_neg <= d_neg_long(PBITS downto PBITS-XBITS);
  r_n_long	<= r * d_neg;
  r_n <= r_n_long(PBITS+XBITS-1 downto XBITS);
  d_n_long <= d * d_neg;
  d_n <= d_n_long(PBITS+XBITS-1 downto XBITS);
end  behavioural;

-----------------------------------------------------------------------------
-- VHDL Test Bench for Goldschmidt inverter
--
-- Exhaustive Analysis
-- Notes: 		
--
-----------------------------------------------------------------------------
LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.mypackage.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY testbench_goldschmidt IS
END testbench_goldschmidt;

ARCHITECTURE behavior OF testbench_goldschmidt IS 
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

	COMPONENT goldschmidt
	PORT(
	    X: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
	    Y: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
	    Q: out STD_LOGIC_VECTOR (PBITS-1 downto 0)
	    );
	END COMPONENT;

	CONSTANT DELAY: time := 100 ns;
	CONSTANT print_ok: boolean := false;
   SIGNAL A: STD_LOGIC_VECTOR (NBITS-1 downto 0);
   SIGNAL B: STD_LOGIC_VECTOR (NBITS-1 downto 0);
   SIGNAL Q: STD_LOGIC_VECTOR (PBITS-1 downto 0);

BEGIN

   uut: goldschmidt PORT MAP( X => A, Y => B, Q => Q );

   tb_test : PROCESS
	VARIABLE TX_LOC : LINE;
	VARIABLE TX_STR : String(1 to 4096);
	Variable iQ: natural;
	Variable dif: integer;
   BEGIN
		WAIT FOR 10 ns;
		for I in 2**(NBITS-1) to 2**NBITS-1 loop
		  for J in I to 2**NBITS-1 loop
				A <= CONV_STD_LOGIC_VECTOR (I, NBITS);
				B <= CONV_STD_LOGIC_VECTOR (J, NBITS);
				WAIT FOR DELAY/2;
			   iQ := CONV_INTEGER(Q);
				dif := (2**(PBITS)*I) - iQ*J;
				IF (abs (dif) > 6*j) THEN 
					write(TX_LOC,string'("Error!!! -> A=")); write(TX_LOC, A);
					write(TX_LOC,string'(" B=")); write(TX_LOC, B);
					write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
					write(TX_LOC,string'(" (i=")); write(TX_LOC, i);
					write(TX_LOC,string'(" j=")); write(TX_LOC, j);
					write(TX_LOC,string'(" iQ=")); write(TX_LOC, iQ);
					write(TX_LOC,string'(" j*iQ=")); write(TX_LOC, iQ*J);
					write(TX_LOC,string'(" dif=")); write(TX_LOC, dif);
					write(TX_LOC, string'(") "));
					TX_STR(TX_LOC.all'range) := TX_LOC.all;
					writeline(results, TX_LOC);
					Deallocate(TX_LOC);
					ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				END IF;
				WAIT FOR DELAY/2;
		end loop;
   	end loop;
		ASSERT (FALSE) REPORT
		"Simulation successful (not a failure).  No problems detected. "
		SEVERITY FAILURE;
   END PROCESS;

END;