-------------------------------------
-- Define the datapath width
--
-------------------------------------
package mypackage is
	constant NBITS :INTEGER := 6;
	constant PBITS :INTEGER := 8;
end mypackage;

---------------------------------------------------------------
-- SRT radix 2 
-- X and Y positives, 0.25 < X < 0.5 and Y > 0.5
-- i.e.: X(NBITS-1) = 0, X(NBITS-2) = 1, and X(NBITS-1) = 1
-- 
---------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;
library UNISIM;
use UNISIM.ALL;

entity div_SRT_r2 is
    port (
        X: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        Y: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        Q: out STD_LOGIC_VECTOR (PBITS-1 downto 0);
		R: out STD_LOGIC_VECTOR (NBITS-1 downto 0)
     );
end div_SRT_r2;

architecture srt_arch of div_SRT_r2 is

component srt_step_r2 is
    port (
        r: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        y: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        q_pos, q_neg: out STD_LOGIC;
		  r_n: out STD_LOGIC_VECTOR (NBITS-1 downto 0)
     );
end component;

type conections is array (0 to PBITS) of STD_LOGIC_VECTOR (NBITS-1 downto 0);
Signal wires: conections;
signal adjust: STD_LOGIC;					 
signal Q_pos, Q_neg: STD_LOGIC_VECTOR (PBITS-1 downto 0);

begin

 wires(0) <= X;
 divisor: for I in 0 to PBITS-1 generate
    int_mod: srt_step_r2 port map (r => wires(i),
  			 y => Y, 
  			 q_neg => Q_neg(PBITS-I-1),
  			 q_pos => Q_pos(PBITS-I-1),
			 r_n => wires(i+1) );
  end generate;

  adjust <= (wires(PBITS)(NBITS-1));
  
  correction_step: process (adjust, wires(PBITS)) 
  begin
    if adjust = '0' then 
	   R <= wires(PBITS)(NBITS-1 downto 0);
    else
	   R <= wires(PBITS)(NBITS-1 downto 0) + Y;
    end if;
  end process;

  Q <= Q_pos - Q_neg - adjust;

end srt_arch;

--------------------------------------------------------
-- srt radix 2 division cell	 
-- 
--------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.mypackage.all;
library UNISIM;
use UNISIM.ALL;

entity srt_step_r2 is
    port (
        r: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        y: in STD_LOGIC_VECTOR (NBITS-1 downto 0);
        q_pos, q_neg: out STD_LOGIC;
		  r_n: out STD_LOGIC_VECTOR (NBITS-1 downto 0)
     );
end srt_step_r2;

architecture behavioural of srt_step_r2 is
signal r_x_2 : STD_LOGIC_VECTOR (NBITS-1 downto 0);
begin

r_x_2	<= r(NBITS-2 downto 0) & '0';

adder_subtracter: process (r,y,r_x_2)
begin
	case r(NBITS-1 downto NBITS-2) is
      when "00" => r_n <= r_x_2;       q_pos <= '0'; q_neg <= '0';
		when "01" => r_n <= r_x_2 - y;	q_pos <= '1'; q_neg <= '0';
		when "10" => r_n <= r_x_2 + y;	q_pos <= '0'; q_neg <= '1';
		when "11" => r_n <= r_x_2;       q_pos <= '0'; q_neg <= '0';
		when others => NULL;
   end case;
end process;

end behavioural;

architecture srt_cel_arch of srt_step_r2 is
signal r_x_2, y_and : STD_LOGIC_VECTOR (NBITS-1 downto 0);
signal q_n, q_p, r_xor : STD_LOGIC;

begin

r_xor <= r(NBITS-1) xor r(NBITS-2);
q_n <= r_xor and r(NBITS-1);
q_p <= r_xor and r(NBITS-2);
r_x_2	<= r(NBITS-2 downto 0) & '0';
ands_Y: for i in 0 to NBITS-1 generate
  Y_and(i) <= y(i) and r_xor;
end generate;

adder_subtracter: process (q_p,Y_and,r_x_2)
begin
  if q_p = '0' then
    r_n <= r_x_2 + Y_and ;
  else
    r_n <= r_x_2 - Y_and ;
  end if;
end process;
q_pos <= q_p;
q_neg <= q_n;
end srt_cel_arch;

----------------------------------------------------------------------
-- VHDL Test Bench for SRT radix 2 divider
--
-- Notes: 
----------------------------------------------------------------------
LIBRARY  IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.mypackage.all;

LIBRARY ieee;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_exhaustive IS
END test_exhaustive;

ARCHITECTURE behavioural OF test_exhaustive IS 
constant DELAY: time := 100 ns;
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";

	COMPONENT div_SRT_r2
	PORT(
		x : IN std_logic_vector(NBITS-1 downto 0);
		y : IN std_logic_vector(NBITS-1 downto 0);
		q : OUT std_logic_vector(PBITS-1 downto 0);
		r : OUT std_logic_vector(NBITS-1 downto 0)
		);
	END COMPONENT;

	SIGNAL x :  std_logic_vector(NBITS-1 downto 0);
	SIGNAL y :  std_logic_vector(NBITS-1 downto 0);
	SIGNAL q :  std_logic_vector(PBITS-1 downto 0);
	SIGNAL r :  std_logic_vector(NBITS-1 downto 0);

BEGIN

	uut: div_SRT_r2 PORT MAP(x => x, y => y, q => q, r => r);

   tb_test : PROCESS
	VARIABLE TX_LOC : LINE;
	VARIABLE TX_STR : String(1 to 4096);
   BEGIN
		for I in 2**(NBITS-2)  to (2**(NBITS-1))-1 loop
			for J in 2**(NBITS-1) to 2**NBITS-1 loop
				x <= CONV_STD_LOGIC_VECTOR (I, NBITS);
				y <= CONV_STD_LOGIC_VECTOR (J, NBITS);
				WAIT FOR DELAY/2;

				IF ((I*(2**(PBITS))) /= (J * CONV_INTEGER(Q)) + CONV_INTEGER(R)) THEN 
					write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, X);
					write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
					write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
					write(TX_LOC,string'(" R=")); write(TX_LOC, R);
					write(TX_LOC, string'(" "));
					TX_STR(TX_LOC.all'range) := TX_LOC.all;
					writeline(results, TX_LOC);
					Deallocate(TX_LOC);
					ASSERT (FALSE) REPORT TX_STR SEVERITY FAILURE;
			   ELSIF (J < CONV_INTEGER(R)) THEN 
						write(TX_LOC,string'("--> Remiander grater than Y =")); write(TX_LOC, 0.0);
						write(TX_LOC,string'("ns X=")); write(TX_LOC, X);
						write(TX_LOC,string'(" Y=")); write(TX_LOC, Y);
						write(TX_LOC,string'(" Q=")); write(TX_LOC, Q);
						write(TX_LOC,string'(" R=")); write(TX_LOC, R);
						write(TX_LOC, string'(" "));
						TX_STR(TX_LOC.all'range) := TX_LOC.all;		
						writeline(results, TX_LOC);
						Deallocate(TX_LOC);
						ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				END IF;
				WAIT FOR DELAY/2;
    		end loop;
   	end loop;
		ASSERT (FALSE) REPORT
		"Simulation successful (not a failure).  No problems detected. "
		SEVERITY FAILURE;
   END PROCESS;
END;