package mypackage is
constant n: natural := 64;
constant delay: time := 1 ns;
constant logn: natural := 3;
end mypackage;

library ieee; use ieee.std_logic_1164.all;
use work.mypackage.all;
entity example10_6 is
port 
(x, y: in std_logic_vector(n-1 downto 0);
c_in, start: in std_logic;
z: out std_logic_vector(n-1 downto 0);
c_out, done: out std_logic
);
end example10_6;

architecture circuit of example10_6 is
signal p, g, k: std_logic_vector(n-1 downto 0);
signal q, qb: std_logic_vector(n downto 0);
--signal int_done: std_logic_vector(1 to n);
begin
q(0) <=  c_in; qb(0) <=  not(c_in) after delay;
iterative_step: for i in 0 to n-1 generate
p(i) <= start and (x(i) xor y(i)) after delay;
g(i) <= start and y(i) after delay;
k(i) <= start and not(y(i)) after delay;
with p(i) select q(i+1) <= q(i) after delay when '1', g(i) after delay when others;
with p(i) select qb(i+1) <= qb(i) after delay when '1', k(i) after delay when others;
z(i) <= p(i) xor q(i) after delay;
end generate;
process(q, qb)
variable accumulator: std_logic;
begin
accumulator := q(1) or qb(1);
for i in 2 to n loop
accumulator := accumulator and (q(i) or qb(i));
end loop;
done <= accumulator after (logn *delay); 
end process;
c_out <= q(n);
end circuit;

library ieee; use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example10_6 is end test_example10_6;

architecture test of test_example10_6 is
component example10_6 is
port 
(x, y: in std_logic_vector(n-1 downto 0);
c_in, start: in std_logic;
z: out std_logic_vector(n-1 downto 0);
c_out, done: out std_logic
);
end component;
signal x, y, z: std_logic_vector(n-1 downto 0);
signal c_in, c_out, start, done: std_logic;
begin
device_under_test: example10_6 port map(x, y, c_in, start, z, c_out, done);
--x <= "1000100111110010111110011111101001011010011111110001100110011101", 
--"1101100001110010110110011111000001011110011111110001100110011010" after 200 ns,
--"1111111111111111111111111111111111111111111111111111111111111111" after 400 ns; 
--y <="1101100001110010110110011111000001011110011111110001100110011001",
--"1111111111111111111111111111111111111111111111111111111111111111" after 200 ns;
x <=X"A03EFCB177896D4F",  X"9999999999999999" after 200 ns, X"FFFFFFFFFFFFFFFF" after 400 ns; 
y <=X"CD3768998DEFF987",  X"6666666666666666" after 200 ns, X"FFFFFFFFFFFFFFFF" after 400 ns;
c_in <= '0', '1' after 200 ns;
start <= '0', '1' after 15 ns, '0' after 190 ns, '1' after 205 ns, '0' after 390 ns, '1' after 405 ns;
end test;