library ieee; use ieee.std_logic_1164.all; package mypackage is constant B: natural := 10; subtype digit is natural range 0 to B-1; type digit_vector is array (natural range <>) of digit; constant n: natural := 8; constant m: natural := 4; constant logm: natural := 2; type operands is array(m-1 downto 0) of digit_vector(n-1 downto 0); constant zero: digit_vector(n-1 downto 0) := (others => 0); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_11 is port (x: in operands; clk, start, reset: in std_logic; done: out std_logic; u: inout digit_vector(n-1 downto 0); v: inout std_logic_vector(n-1 downto 0) ); end example11_11; architecture circuit of example11_11 is signal op_1, reg_in_u: digit_vector(n-1 downto 0); signal reg_in_v: std_logic_vector(n-1 downto 0); signal operand_select: std_logic_vector(logm-1 downto 0); signal load, clear: std_logic; subtype state is integer range -3 to m; signal current_state: state; begin --data path: op_1 <= x(conv_integer(operand_select)); reg_in_v(0) <= '0'; encoder: for i in 0 to n-2 generate reg_in_v(i+1) <= '0' when op_1(i) + u(i) + conv_integer(v(i)) < B else '1'; reg_in_u(i) <= (op_1(i) + u(i) + conv_integer(v(i))) mod B; end generate; reg_in_u(n-1) <= (op_1(n-1) + u(n-1) + conv_integer(v(n-1))) mod B; process(clk) begin if clear = '1' then u <= zero; v <= (others => '0'); elsif clk'event and clk = '1' then if load = '1' then u <= reg_in_u; v <= reg_in_v; end if; end if; end process; --control unit process(clk, reset) begin case current_state is when -3 => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when -2 => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when -1 => load <= '0'; clear <= '1'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; when 0 to m-1 => load <= '1'; clear <= '0'; operand_select <= conv_std_logic_vector(current_state, logm); done <= '0'; when m => load <= '0'; clear <= '0'; operand_select <= conv_std_logic_vector(0, logm); done <= '1'; end case; if reset = '1' then current_state <= -3 ; elsif clk'event and clk = '1' then case current_state is when -3 => if start = '0' then current_state <= current_state + 1; end if; when -2 => if start = '1' then current_state <= current_state + 1; end if; when -1 => current_state <= current_state + 1; when 0 to m-1 => current_state <= current_state + 1; when m => current_state <= -3 ; end case; end if; end process; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_11 is end test_example11_11; architecture test of test_example11_11 is component example11_11 port (x: in operands; clk, start, reset: in std_logic; done: out std_logic; u: inout digit_vector(n-1 downto 0); v: inout std_logic_vector(n-1 downto 0) ); end component; signal x: operands; signal u: digit_vector(n-1 downto 0); signal v: std_logic_vector(n-1 downto 0); signal clk, start, reset: std_logic := '0'; signal done: std_logic; begin device_under_test: example11_11 port map(x, clk, start, reset, done, u, v); x(0) <= (7,9,1,2,8,3,7,0), (9,1,9,2,9,3,9,7) after 150 ns, (9,9,9,9,9,9,9,9) after 300 ns; x(1) <= (2,1,2,5,4,8,2,6), (7,7,4,6,2,2,5,4) after 150 ns, (9,9,9,9,9,9,9,9) after 300 ns; x(2) <= (1,3,1,1,1,5,4,6), (9,8,7,6,5,4,3,2) after 150 ns, (9,9,9,9,9,9,9,9) after 300 ns; x(3) <= (0,0,2,4,3,4,5,2), (1,2,6,5,3,4,9,8) after 150 ns, (9,9,9,9,9,9,9,9) after 300 ns; clk <= not(clk) after 5 ns; reset <= '1', '0' after 10 ns; start <= '0', '1' after 20 ns, '0' after 40 ns, '1' after 200 ns, '0' after 220ns, '1' after 400 ns; end test;