library ieee; use ieee.std_logic_1164.all;
package mypackage is
constant B: natural := 10;
subtype digit is natural range 0 to B-1;
type digit_vector is array (natural range <>) of digit;
constant n: natural := 4;
end mypackage;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity example11_13 is
port 
(x, y: in digit_vector(n-1 downto 0);
control, d_in: in std_logic;
z: out digit_vector(n-1 downto 0);
d_out: out std_logic
);
end example11_13;

architecture circuit of example11_13 is
signal minus_y, operand_2: digit_vector(n-1 downto 0);
signal carries: std_logic_vector(n downto 0);

begin
invert: for i in 0 to n-1 generate minus_y(i) <= B-1-y(i); end generate;
with control select operand_2 <= y when '0', minus_y when others;

carries(0) <= control xor d_in;
adder: for i in 0 to n-1 generate
iterative_step:
z(i) <= (x(i) + operand_2(i) + conv_integer(carries(i))) mod B;
carries(i+1) <= '0' when x(i) + operand_2(i) + conv_integer(carries(i)) < B else '1';
end generate;

d_out <= carries(n) xor control;

end circuit;


library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example11_13 is end test_example11_13;

architecture test of test_example11_13 is
component example11_13
port 
(x, y: in digit_vector(n-1 downto 0);
control, d_in: in std_logic;
z: out digit_vector(n-1 downto 0);
d_out: out std_logic
);
end component;

signal x, y, z: digit_vector(n-1 downto 0);
signal control, d_in, d_out: std_logic;

begin
device_under_test: example11_13 port map(x, y, control, d_in, z, d_out);
x <= (2,3,4,5), (7,2,1,1) after 200 ns;
y <= (6,6,7,4), (7,2,7,4) after 100 ns, (4,2,1,0) after 200 ns, (8,2,0,9) after 300 ns;
d_in <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
control <= '0', '1' after 200 ns;
end test;