library ieee; use ieee.std_logic_1164.all;
package mypackage is
constant B: natural := 10;
subtype digit is natural range 0 to B-1;
type digit_vector is array (natural range <>) of digit;
constant n: natural := 4;
end mypackage;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity example11_15 is
port 
(x, y: in digit_vector(n-1 downto 0);
control, d_in: in std_logic;
z: out digit_vector(n downto 0)
);
end example11_15;

architecture circuit of example11_15 is
signal minus_y, operand_2: digit_vector(n-1 downto 0);
signal carries: std_logic_vector(n downto 0);
signal x_n, operand_2_n: digit;

begin

invert: for i in 0 to n-1 generate minus_y(i) <= B-1-y(i); end generate;
with control select operand_2 <= y when '0', minus_y when others;

x_n <= 0 when x(n-1) < B/2 else B-1;
operand_2_n <= 0 when operand_2(n-1) < B/2 else B-1;

carries(0) <= control xor d_in;

adder: for i in 0 to n-1 generate
iterative_step:
z(i) <= (x(i) + operand_2(i) + conv_integer(carries(i))) mod B;
carries(i+1) <= '0' when x(i) + operand_2(i) + conv_integer(carries(i)) < B else '1';
end generate;

z(n) <= (x_n + operand_2_n + conv_integer(carries(n))) mod B;

end circuit;


library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example11_15 is end test_example11_15;

architecture test of test_example11_15 is
component example11_15
port 
(x, y: in digit_vector(n-1 downto 0);
control, d_in: in std_logic;
z: out digit_vector(n downto 0)
);
end component;

signal x, y: digit_vector(n-1 downto 0);
signal z: digit_vector(n downto 0);
signal control, d_in: std_logic;

begin
device_under_test: example11_15 port map(x, y, control, d_in, z);
x <= (2,3,4,5), (7,2,1,1) after 400 ns;
y <= (4,6,7,4), (9,2,7,4) after 100 ns, (4,2,1,0) after 300 ns, 
(4,6,7,4) after 400 ns, (9,2,7,4) after 500 ns, (4,2,1,0) after 700 ns;
d_in <= '0', '1' after 100 ns, '0' after 200 ns, '1' after 300 ns;
control <= '0', '1' after 200 ns;
end test;