package mypackage is
constant n: natural := 6;
constant B: natural := 10;
subtype digit is natural range 0 to B-1;
type digit_vector is array (natural range <>) of digit;
end mypackage;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity example10_2 is
port 
(x, y: in digit_vector(n-1 downto 0);
c_in: in std_logic;
z: out digit_vector(n-1 downto 0);
c_out: out std_logic
);
end example10_2;

architecture circuit of example10_2 is
signal p, g: std_logic_vector(n-1 downto 0);
signal q: std_logic_vector(n downto 0);
begin
q(0) <= c_in;
iterative_step: for i in 0 to n-1 generate
p(i) <= '1' when x(i) + y(i) = B-1 else '0';
g(i) <= '1' when x(i) + y(i) > B-1 else'0';
with p(i) select q(i+1) <= q(i) when '1', g(i) when others;
z(i) <= (x(i) + y(i) + conv_integer(q(i))) mod B;
end generate;
c_out <= q(n);
end circuit;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example10_2 is end test_example10_2;

architecture test of test_example10_2 is
component example10_2
port 
(x, y: in digit_vector(n-1 downto 0);
c_in: in std_logic;
z: out digit_vector(n-1 downto 0);
c_out: out std_logic
);
end component;
signal x, y, z: digit_vector(n-1 downto 0);
signal c_in, c_out: std_logic;
begin
device_under_test: example10_2 port map(x, y, c_in, z, c_out);
x <= (4,9,7,4,3,9), (9,9,9,9,9,2) after 10 ns;
y <= (1,0,0,4,6,1), (2,7,9,1,7,2) after 30 ns;
c_in <= '0', '1' after 15 ns;
end test;