package mypackage is constant s: natural := 2; constant n_div_s: natural := 4; constant n: natural := s * n_div_s; constant B: natural := 10; subtype digit is natural range 0 to B-1; type digit_vector is array (natural range <>) of digit; end mypackage; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity carry_skip is port (x, y: in digit_vector(s-1 downto 0); c_in: in std_logic; c_out: out std_logic_vector(s downto 1) ); end carry_skip; architecture circuit of carry_skip is signal p, g: std_logic_vector(s-1 downto 0); signal generalized_p: std_logic; signal q: std_logic_vector(s downto 0); begin q(0) <= c_in; iterative_step: for i in 0 to s-1 generate p(i) <= '1' when x(i) + y(i) = B-1 else '0'; g(i) <= '1' when x(i) + y(i) > B-1 else'0'; with p(i) select q(i+1) <= q(i) when '1', g(i) when others; end generate; process(p) variable accumulator: std_logic; begin accumulator := p(0); for i in 1 to s-1 loop accumulator := accumulator and p(i); end loop; generalized_p <= accumulator; end process; with generalized_p select c_out(s) <= c_in when '1', q(s) when others; carries: for i in 1 to s-1 generate c_out(i) <= q(i); end generate; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_3 is port (x, y: in digit_vector(n-1 downto 0); c_in: in std_logic; z: out digit_vector(n-1 downto 0); c_out: out std_logic ); end example11_3; architecture circuit of example11_3 is component carry_skip port (x, y: in digit_vector(s-1 downto 0); c_in: in std_logic; c_out: out std_logic_vector(s downto 1) ); end component; signal q: std_logic_vector(n downto 0); begin q(0) <= c_in; ext_iteration: for i in 0 to n_div_s - 1 generate carry_chain: carry_skip port map(x(i*s+s-1 downto i*s), y(i*s+s-1 downto i*s), q(i*s), q(i*s+s downto i*s+1)); int_iteration: for j in 0 to s-1 generate z(i*s+j) <= (x(i*s+j) + y(i*s+j) + conv_integer(q(i*s+j))) mod B; end generate; end generate; c_out <= q(n); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_3 is end test_example11_3; architecture test of test_example11_3 is component example11_3 port (x, y: in digit_vector(n-1 downto 0); c_in: in std_logic; z: out digit_vector(n-1 downto 0); c_out: out std_logic ); end component; signal x, y: digit_vector(n-1 downto 0); signal c_in: std_logic; signal z: digit_vector(n-1 downto 0); signal c_out: std_logic; begin device_under_test: example11_3 port map(x, y, c_in, z, c_out); x <= (4,9,7,5,3,9,2,6), (9,0,7,5,3,8,2,6) after 10 ns; y <= (0,9,2,4,6,1,7,3), (0,9,3,4,6,1,7,3) after 30 ns, (0,9,2,4,5,0,6,2) after 40 ns; c_in <= '0', '1' after 15 ns; end test;