library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; package mypackage is constant n: natural := 16; constant n_div_2: natural := n/2; --constant n_div_4: natural := n/4; --constant n_div_8: natural := n/8; constant B: natural := 10; subtype digit is natural range 0 to B-1; type digit_vector is array (natural range <>) of digit; procedure dot_operation(g1, p1, g0, p0: in std_logic; signal gg, pp: out std_logic); end mypackage; package body mypackage is procedure dot_operation(g1, p1, g0, p0: in std_logic; signal gg, pp: out std_logic) is begin gg <= g1 or (g0 and p1); pp <= p1 and p0; end procedure; end mypackage; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity prefix_2 is port ( g, p: in std_logic_vector(1 downto 0); gg, pp: out std_logic_vector(1 downto 0) ); end prefix_2; architecture circuit of prefix_2 is begin dot_operation(g(1), p(1), g(0), p(0), gg(1), pp(1)); gg(0) <= g(0); pp(0) <= p(0); end circuit; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity prefix_4 is port ( g, p: in std_logic_vector(3 downto 0); gg, pp: out std_logic_vector(3 downto 0) ); end prefix_4; architecture circuit of prefix_4 is component prefix_2 port ( g, p: in std_logic_vector(1 downto 0); gg, pp: out std_logic_vector(1 downto 0) ); end component; signal a, b, aa, bb: std_logic_vector(1 downto 0); begin first_iteration: for i in 0 to 1 generate dot_operation(g(2*i+1), p(2*i+1), g(2*i), p(2*i), a(i), b(i)); end generate; component_instantiation: prefix_2 port map (a, b, aa, bb); --second_iteration: dot_operation(g(2), p(2), aa(0), bb(0), gg(2), pp(2)); gg(0) <= g(0); pp(0) <= p(0); third_iteration: for i in 0 to 1 generate gg(2*i+1) <= a(i); pp(2*i+1) <= b(i); end generate; end circuit; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity prefix_n_div_2 is port ( g, p: in std_logic_vector(n_div_2 - 1 downto 0); gg, pp: out std_logic_vector(n_div_2 - 1 downto 0) ); end prefix_n_div_2; architecture circuit of prefix_n_div_2 is --component prefix_n_div_4 component prefix_4 port ( --g, p: in std_logic_vector(n_div_4 - 1 downto 0); --gg, pp: out std_logic_vector(n_div_4 - 1 downto 0) g, p: in std_logic_vector(3 downto 0); gg, pp: out std_logic_vector(3 downto 0) ); end component; --signal a, b, aa, bb: std_logic_vector(n_div_4 - 1 downto 0); signal a, b, aa, bb: std_logic_vector(3 downto 0); begin --first_iteration: for i in 0 to n_div_4 - 1 generate first_iteration: for i in 0 to 3 generate dot_operation(g(2*i+1), p(2*i+1), g(2*i), p(2*i), a(i), b(i)); end generate; --component_instantiation: prefix_n_div_4 port map (a, b, aa, bb); component_instantiation: prefix_4 port map (a, b, aa, bb); --second_iteration: for i in 1 to n_div_4 - 1 generate second_iteration: for i in 1 to 2 generate dot_operation(g(2*i), p(2*i), aa(i-1), bb(i-1), gg(2*i), pp(2*i)); end generate; gg(0) <= g(0); pp(0) <= p(0); --third_iteration: for i in 0 to n_div_4 - 1 generate third_iteration: for i in 0 to 3 generate gg(2*i+1) <= a(i); pp(2*i+1) <= b(i); end generate; end circuit; library ieee; use ieee.std_logic_1164.all; --use ieee.std_logic_arith.all; --use ieee.std_logic_unsigned.all; use work.mypackage.all; entity prefix_n is port ( g, p: in std_logic_vector(n-1 downto 0); gg, pp: out std_logic_vector(n-1 downto 0) ); end prefix_n; architecture circuit of prefix_n is component prefix_n_div_2 port ( g, p: in std_logic_vector(n_div_2 - 1 downto 0); gg, pp: out std_logic_vector(n_div_2 - 1 downto 0) ); end component; signal a, b, aa, bb: std_logic_vector(n_div_2 - 1 downto 0); begin first_iteration: for i in 0 to n_div_2 - 1 generate dot_operation(g(2*i+1), p(2*i+1), g(2*i), p(2*i), a(i), b(i)); end generate; component_instantiation: prefix_n_div_2 port map (a, b, aa, bb); second_iteration: for i in 1 to n_div_2 - 1 generate dot_operation(g(2*i), p(2*i), aa(i-1), bb(i-1), gg(2*i), pp(2*i)); end generate; gg(0) <= g(0); pp(0) <= p(0); third_iteration: for i in 0 to n_div_2 - 1 generate gg(2*i+1) <= a(i); pp(2*i+1) <= b(i); end generate; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity example11_9 is port (x, y: in digit_vector(n-1 downto 0); c_in: in std_logic; z: out digit_vector(n-1 downto 0); c_out: out std_logic ); end example11_9; architecture circuit of example11_9 is component prefix_n port ( g, p: in std_logic_vector(n-1 downto 0); gg, pp: out std_logic_vector(n-1 downto 0) ); end component; signal p, g, pp, gg: std_logic_vector(n-1 downto 0); signal q: std_logic_vector(n downto 0); begin q(0) <= c_in; iterative_step: for i in 0 to n-1 generate p(i) <= '1' when x(i) + y(i) = B-1 else '0'; g(i) <= '1' when x(i) + y(i) > B-1 else'0'; z(i) <= (x(i) + y(i) + conv_integer(q(i))) mod B; end generate; component_instantiation: prefix_n port map(g, p, gg, pp); carry_computation: for i in 1 to n generate q(i) <= gg(i-1) or (pp(i-1) and q(i-1)); end generate; c_out <= q(n); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_example11_9 is end test_example11_9; architecture test of test_example11_9 is component example11_9 port (x, y: in digit_vector(n-1 downto 0); c_in: in std_logic; z: out digit_vector(n-1 downto 0); c_out: out std_logic ); end component; signal x, y: digit_vector(n-1 downto 0); signal c_in: std_logic; signal z: digit_vector(n-1 downto 0); signal c_out: std_logic; begin device_under_test: example11_9 port map(x, y, c_in, z, c_out); x <= (4,9,7,5,3,9,2,6,9,0,7,5,3,8,2,6), (4,9,7,5,3,9,2,6,9,0,7,5,3,8,2,6) after 10 ns; y <= (0,9,2,4,6,1,7,3,0,9,3,4,6,1,7,3), (7,9,2,4,5,0,6,2,0,9,2,4,6,1,7,3) after 20 ns, (7,4,9,3,4,6,9,7,6,6,5,8,2,4,1,1) after 30 ns; c_in <= '0', '1' after 15 ns; end test;