package mypackage is
constant n: natural := 8;
constant m: natural := 239;
end mypackage;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity mod_adder is
port 
(x, y: in std_logic_vector(n-1 downto 0);
z: out std_logic_vector(n-1 downto 0)
);
end mod_adder;

architecture circuit of mod_adder is
signal z1, z2: std_logic_vector(n-1 downto 0);
signal c1, c2: std_logic;
signal long_x, long_y, long_result1, long_z1, minus_m, long_result2: std_logic_vector(n downto 0);
begin
long_x <= '0'&x;
long_y <= '0'&y;
long_result1 <= long_x + long_y;
c1 <= long_result1(n);
z1 <= long_result1(n-1 downto 0);
long_z1 <= '0'&z1;
minus_m <=  conv_std_logic_vector((2**n)-m, n+1);
long_result2 <= long_z1 + minus_m;
c2 <= long_result2(n);
z2 <= long_result2(n-1 downto 0);
z <= z1 when (c1 or c2) = '0' else z2;
end circuit;

library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity mod_subtractor is
port 
(x, y: in std_logic_vector(n-1 downto 0);
z: out std_logic_vector(n-1 downto 0)
);
end mod_subtractor;

architecture circuit of mod_subtractor is
signal z1, z2, inv_y: std_logic_vector(n-1 downto 0);
signal c1: std_logic;
signal long_x, long_inv_y, long_result1: std_logic_vector(n downto 0);
begin
long_x <= '0'&x;
--long_y <= '0'&y;
inversion: for i in 0 to n-1 generate inv_y(i) <= not(y(i)); end generate;
long_inv_y <= '0'&inv_y;
long_result1 <= long_x + long_inv_y + '1';
c1 <= long_result1(n);
z1 <= long_result1(n-1 downto 0);
z2 <= z1 + conv_std_logic_vector(m, n);
z <= z1 when c1 = '1' else z2;
end circuit;



library ieee; use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.mypackage.all;
entity test_example15_1 is end test_example15_1;

architecture test of test_example15_1 is
component mod_adder
port 
(x, y: in std_logic_vector(n-1 downto 0);
z: out std_logic_vector(n-1 downto 0)
);
end component;
component mod_subtractor
port 
(x, y: in std_logic_vector(n-1 downto 0);
z: out std_logic_vector(n-1 downto 0)
);
end component;
signal x, y, sum, difference: std_logic_vector(n-1 downto 0);
begin
device_under_test_1: mod_adder port map(x, y, sum);
device_under_test_2: mod_subtractor port map(x, y, difference);
x <= conv_std_logic_vector(227, n), 
conv_std_logic_vector(14, n) after 10 ns, 
conv_std_logic_vector(210, n) after 20 ns,
conv_std_logic_vector(45, n) after 30 ns,
conv_std_logic_vector(0, n) after 40 ns,
conv_std_logic_vector(238, n) after 50 ns,
conv_std_logic_vector(238, n) after 60 ns;
y <= conv_std_logic_vector(198, n), 
conv_std_logic_vector(211, n) after 10 ns, 
conv_std_logic_vector(46, n) after 20 ns,
conv_std_logic_vector(126, n) after 30 ns,
conv_std_logic_vector(0, n) after 40 ns,
conv_std_logic_vector(0, n) after 50 ns,
conv_std_logic_vector(238, n) after 60 ns;
end test;