library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 8; constant m: natural := 239; type p_vector is array(0 to n) of std_logic_vector(n-1 downto 0); constant zero: std_logic_vector(n-1 downto 0) := ('0', others => '0'); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity iterative_step is port (p, k: in std_logic_vector(n-1 downto 0); x: in std_logic; next_p: out std_logic_vector(n-1 downto 0) ); end iterative_step; architecture circuit of iterative_step is signal w, module: std_logic_vector(n-1 downto 0); signal sign2, sign3: std_logic; signal p1, long_w, p2: std_logic_vector(n+1 downto 0); signal long_module, p3: std_logic_vector(n downto 0); begin module <= conv_std_logic_vector(m, n); w <= module when x = '0' else k; long_w <= "00"&w; p1 <= '0'&p&'0'; p2 <= p1 - long_w; sign2 <= p2(n+1); long_module <= '0'&module; with sign2 select p3 <= p2(n downto 0) + long_module when '1', p2(n downto 0) - long_module when others; sign3 <= p3(n); next_p <= p2(n-1 downto 0) when sign3 = '1' else p3(n-1 downto 0); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_step is end test_step; architecture test of test_step is component iterative_step port (p, k: in std_logic_vector(n-1 downto 0); x: in std_logic; next_p: out std_logic_vector(n-1 downto 0) ); end component; signal p, k, next_p: std_logic_vector(n-1 downto 0); signal x: std_logic; begin device_under_test: iterative_step port map(p, k, x, next_p); p <= conv_std_logic_vector(227, n), conv_std_logic_vector(14, n) after 10 ns, conv_std_logic_vector(210, n) after 20 ns, conv_std_logic_vector(45, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(238, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; k <= conv_std_logic_vector(198, n), conv_std_logic_vector(211, n) after 10 ns, conv_std_logic_vector(46, n) after 20 ns, conv_std_logic_vector(126, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(0, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; x <= '0', '1' after 10 ns, '0' after 70 ns; end test; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity mod_multiplier is port ( x, y: in std_logic_vector(n-1 downto 0); z: out std_logic_vector(n-1 downto 0) ); end mod_multiplier; architecture circuit of mod_multiplier is component iterative_step port (p, k: in std_logic_vector(n-1 downto 0); x: in std_logic; next_p: out std_logic_vector(n-1 downto 0) ); end component; signal p: p_vector; signal k, module: std_logic_vector(n-1 downto 0); begin module <= conv_std_logic_vector(m, n); k <= module - y; p(0) <= zero; iteration: for i in 0 to n-1 generate step: iterative_step port map (p(i), k, x(n-i-1), p(i+1)); end generate; z <= p(n); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_multiply is end test_multiply; architecture test of test_multiply is component mod_multiplier port ( x, y: in std_logic_vector(n-1 downto 0); z: out std_logic_vector(n-1 downto 0) ); end component; signal x, y, z: std_logic_vector(n-1 downto 0); begin device_under_test: mod_multiplier port map(x, y, z); x <= conv_std_logic_vector(227, n), conv_std_logic_vector(14, n) after 10 ns, conv_std_logic_vector(210, n) after 20 ns, conv_std_logic_vector(45, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(238, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; y <= conv_std_logic_vector(198, n), conv_std_logic_vector(211, n) after 10 ns, conv_std_logic_vector(46, n) after 20 ns, conv_std_logic_vector(126, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(0, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; end test;