library ieee; use ieee.std_logic_1164.all; package mypackage is constant n: natural := 8; constant m: natural := 239; type r_vector is array(0 to n) of std_logic_vector(n downto 0); constant zero: std_logic_vector(n downto 0) := ('0', others => '0'); end mypackage; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity Montgomery_step is port (r: in std_logic_vector(n downto 0); y: in std_logic_vector(n-1 downto 0); x: in std_logic; next_r: out std_logic_vector(n downto 0) ); end Montgomery_step; architecture circuit of Montgomery_step is signal long_r, y_by_x, a, m_by_a, two_r: std_logic_vector(n+1 downto 0); signal module: std_logic_vector(n-1 downto 0); begin long_r <= '0'&r; and_gates1: for i in 0 to n-1 generate y_by_x(i) <= y(i) and x; end generate; y_by_x(n) <= '0'; y_by_x(n+1) <= '0'; a <= long_r + y_by_x; module <= conv_std_logic_vector(m, n); and_gates2: for i in 0 to n-1 generate m_by_a(i) <= module(i) and a(0); end generate; m_by_a(n) <= '0'; m_by_a(n+1) <= '0'; two_r <= a + m_by_a; next_r <= two_r(n+1 downto 1); end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_Mont_step is end test_Mont_step; architecture test of test_Mont_step is component Montgomery_step port (r: in std_logic_vector(n downto 0); y: in std_logic_vector(n-1 downto 0); x: in std_logic; next_r: out std_logic_vector(n downto 0) ); end component; signal r, next_r: std_logic_vector(n downto 0); signal y: std_logic_vector(n-1 downto 0); signal x: std_logic; begin device_under_test: Montgomery_step port map(r, y, x, next_r); r <= conv_std_logic_vector(454, n+1), conv_std_logic_vector(14, n+1) after 10 ns, conv_std_logic_vector(420, n+1) after 20 ns, conv_std_logic_vector(45, n+1) after 30 ns, conv_std_logic_vector(0, n+1) after 40 ns, conv_std_logic_vector(476, n+1) after 50 ns, conv_std_logic_vector(476, n+1) after 60 ns; y <= conv_std_logic_vector(198, n), conv_std_logic_vector(211, n) after 10 ns, conv_std_logic_vector(46, n) after 20 ns, conv_std_logic_vector(126, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(0, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; x <= '0', '1' after 10 ns, '0' after 70 ns; end test; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity Montgomery_multiplier is port ( x, y: in std_logic_vector(n-1 downto 0); z: out std_logic_vector(n-1 downto 0) ); end Montgomery_multiplier; architecture circuit of Montgomery_multiplier is component Montgomery_step port (r: in std_logic_vector(n downto 0); y: in std_logic_vector(n-1 downto 0); x: in std_logic; next_r: out std_logic_vector(n downto 0) ); end component; signal r: r_vector; signal module: std_logic_vector(n-1 downto 0); signal long_r_n, long_module, dif: std_logic_vector(n+1 downto 0); begin module <= conv_std_logic_vector(m, n); r(0) <= zero; iteration: for i in 0 to n-1 generate step: Montgomery_step port map (r(i), y, x(i), r(i+1)); end generate; long_r_n <= '0'&r(n); long_module <= "00"&module; dif <= long_r_n - long_module; with dif(n+1) select z <= dif(n-1 downto 0) when '0', r(n)(n-1 downto 0) when others; end circuit; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; use work.mypackage.all; entity test_Montgomery is end test_Montgomery; architecture test of test_Montgomery is component Montgomery_multiplier port ( x, y: in std_logic_vector(n-1 downto 0); z: out std_logic_vector(n-1 downto 0) ); end component; signal x, y, z, z1, exp_2n: std_logic_vector(n-1 downto 0); begin exp_2n <= conv_std_logic_vector(50, 8); device_under_test1: Montgomery_multiplier port map(x, y, z1); device_under_test2: Montgomery_multiplier port map(z1, exp_2n, z); x <= conv_std_logic_vector(227, n), conv_std_logic_vector(14, n) after 10 ns, conv_std_logic_vector(210, n) after 20 ns, conv_std_logic_vector(45, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(238, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; y <= conv_std_logic_vector(198, n), conv_std_logic_vector(211, n) after 10 ns, conv_std_logic_vector(46, n) after 20 ns, conv_std_logic_vector(126, n) after 30 ns, conv_std_logic_vector(0, n) after 40 ns, conv_std_logic_vector(0, n) after 50 ns, conv_std_logic_vector(238, n) after 60 ns; end test;