-------------------------------------------------------------------------------- -- -- VHDL Test Bench for module: nr_reducer.vhd -- -- If constant N and K are small (N+K < 15) executes an exhaustive Test Bench -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_arith.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; USE ieee.std_logic_textio.ALL; USE std.textio.ALL; use work.nr_reducer_parameters.all; ENTITY test_reduction_vhd IS END test_reduction_vhd; ARCHITECTURE behavior OF test_reduction_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT nr_reducer PORT( x : IN std_logic_vector(N downto 0); m : IN std_logic_vector(K-1 downto 0); clk : IN std_logic; reset : IN std_logic; start : IN std_logic; z : OUT std_logic_vector(K-1 downto 0); done : OUT std_logic ); END COMPONENT; --Inputs SIGNAL clk : std_logic := '0'; SIGNAL reset : std_logic := '0'; SIGNAL start : std_logic := '0'; SIGNAL x : std_logic_vector(N downto 0) := (others=>'0'); SIGNAL m : std_logic_vector(K-1 downto 0) := (others=>'0'); --Outputs SIGNAL z : std_logic_vector(K-1 downto 0); SIGNAL done : std_logic; constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 0 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: nr_reducer PORT MAP( x => x, m => m, clk => clk, reset => reset, start => start, z => z, done => done ); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; tb_gen : PROCESS --generate values VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); BEGIN reset <= '1'; WAIT FOR PERIOD; reset <= '0'; WAIT FOR PERIOD; for J in 2**(K-1) to 2**K-1 loop for I in -2**N to 2**N -1 loop x <= CONV_STD_LOGIC_VECTOR (I, N+1); m <= CONV_STD_LOGIC_VECTOR (J, K); start <= '1'; WAIT FOR PERIOD; start <= '0'; WAIT until (done = '1'); WAIT FOR PERIOD; end loop; end loop; WAIT FOR 3 * PERIOD; END PROCESS; tb_test : PROCESS --test the correctness of data VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); BEGIN ASSERT (K+N < 15) REPORT "K+N is too big for an exhaustive Test Bench." SEVERITY FAILURE; WAIT FOR PERIOD; for J in 2**(K-1) to 2**K-1 loop for I in -2**N to 2**N -1 loop WAIT until (done = '1'); WAIT FOR PERIOD/2; IF ( (I mod J) /= ieee.std_logic_unsigned.CONV_INTEGER(z) ) THEN write(TX_LOC,string'("ERROR!!! X=")); write(TX_LOC, x); write(TX_LOC,string'(" mod M=")); write(TX_LOC, m); write(TX_LOC,string'(" is Z=")); write(TX_LOC, z); write(TX_LOC,string'(" instead of:")); write(TX_LOC, I mod J); write(TX_LOC, string'(" ")); write(TX_LOC,string'(" (i=")); write(TX_LOC, i); write(TX_LOC,string'(" j=")); write(TX_LOC, j); write(TX_LOC, string'(")")); TX_STR(TX_LOC.all'range) := TX_LOC.all; Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; END IF; end loop; end loop; ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; END PROCESS; END;