-------------------------------------------------------------------------------- -- Test for Polynomial adder subtractor (ch5) -- Generates random vectors and comparte results -- -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; USE ieee.std_logic_textio.ALL; use ieee.math_real.all; -- for UNIFORM, TRUNC use work.adder_subt_parameters.all; USE std.textio.ALL; ENTITY test_add_sub_polynom IS END test_add_sub_polynom; ARCHITECTURE behavior OF test_add_sub_polynom IS -- Component Declaration for the Unit Under Test (UUT1) component add_sub_polynom is port( a, b: in polynomial; add_sub: in std_logic; z: out polynomial); end component add_sub_polynom; -- Internal signals constant DELAY : time := 100 ns; constant NUMBER_TESTS: natural := 100; signal x, y, x_minus_y, x_plus_y, xx, yy: polynomial := (others => zero_coef); BEGIN -- Instantiate the Unit Under Test (UUT) uut1: add_sub_polynom PORT MAP(a => x, b => y, add_sub => '1', z => x_minus_y); uut2: add_sub_polynom PORT MAP(a => x_minus_y, b => y, add_sub => '0', z => xx); uut3: add_sub_polynom PORT MAP(a => x, b => y, add_sub => '0', z => x_plus_y); uut4: add_sub_polynom PORT MAP(a => x_plus_y, b => x, add_sub => '1', z => yy); tb_proc : PROCESS --generate values PROCEDURE gen_polynom(X : out polynomial; w: natural; s1, s2: inout Natural) IS VARIABLE i_x, i_p: integer; VARIABLE rand: real; BEGIN i_p := conv_integer(('0' & P)); for i in 0 to M-1 loop UNIFORM(s1, s2, rand); i_x := INTEGER(TRUNC(rand * real(i_p))); X(i) := CONV_STD_LOGIC_VECTOR (i_x, K); end loop; END PROCEDURE; VARIABLE seed1, seed2: positive; VARIABLE aPol: polynomial; VARIABLE i_x: natural; VARIABLE rand: real; BEGIN WAIT FOR DELAY; for I in 1 to NUMBER_TESTS loop gen_polynom(aPol, M, seed1, seed2); x <= aPol; gen_polynom(aPol, M, seed1, seed2); y <= aPol; WAIT FOR DELAY; IF ( (x /= xx) or (y /= yy) ) THEN ASSERT (FALSE) REPORT "ERROR!!! X-Y+Y /= X or X+Y-X /= Y" SEVERITY ERROR; END IF; end loop; WAIT FOR DELAY; ASSERT (FALSE) REPORT "Simulation successful!. Not error detected" SEVERITY FAILURE; END PROCESS; END;