-------------------------------------------------------------------------------- -- Test for mastrovito trinomials (ch7) -- Generates random vectors and comparte resutls -- -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.std_logic_arith.all; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; USE ieee.std_logic_textio.ALL; use ieee.math_real.all; -- for UNIFORM, TRUNC USE std.textio.ALL; ENTITY test_mult_trinom IS END test_mult_trinom; ARCHITECTURE behavior OF test_mult_trinom IS -- Component Declaration for the Unit Under Test (UUT1) COMPONENT interleaved_mult_F is generic (M: natural:= 8); port ( A: in std_logic_vector(M-1 downto 0); B: in std_logic_vector(M-1 downto 0); F: in std_logic_vector(M-1 downto 0); clk, reset, start: in std_logic; Z: out std_logic_vector (M-1 downto 0); done: out std_logic ); END COMPONENT; -- Component Declaration for the Unit Under Test (UUT2) COMPONENT mastrovito_trinom_multiplication is generic(M : natural := 8; K: natural := 3); port ( a, b: in std_logic_vector(M-1 downto 0); c: out std_logic_vector(M-1 downto 0) ); END COMPONENT mastrovito_trinom_multiplication; -- Internal signals constant M: natural := 8; constant K: natural := 4; constant F: std_logic_vector(M-1 downto 0) := (0 => '1', K=> '1',others=>'0'); SIGNAL x, y, z, c : std_logic_vector(M-1 downto 0) := (others=>'0'); SIGNAL clk, reset, start, done: std_logic; constant DELAY : time := 100 ns; constant PERIOD : time := 200 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 0 ns; constant NUMBER_TESTS: natural := 1000; BEGIN -- Instantiate the Unit Under Test (UUT) uut1: interleaved_mult_F PORT MAP(A => x, B => y, F => F, clk => clk, reset => reset, start => start, z => z, done => done); uut2: mastrovito_trinom_multiplication generic map(M => M, K => K) PORT MAP(A => x, B => y, c => c); PROCESS -- clock process for clk BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP clk <= '0'; WAIT FOR (PERIOD *(1.0 - DUTY_CYCLE)); clk <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; tb_proc : PROCESS --generate values PROCEDURE gen_random(X : out std_logic_vector (M-1 DownTo 0); w: natural; s1, s2: inout Natural) IS VARIABLE i_x, aux: integer; VARIABLE rand: real; BEGIN aux := W/16; for i in 1 to aux loop UNIFORM(s1, s2, rand); i_x := INTEGER(TRUNC(rand * real(2**16))); x(i*16-1 downto (i-1)*16) := CONV_STD_LOGIC_VECTOR (i_x, 16); end loop; UNIFORM(s1, s2, rand); i_x := INTEGER(TRUNC(rand * real(2**(w-aux*16)))); x(w-1 downto aux*16) := CONV_STD_LOGIC_VECTOR (i_x, (w-aux*16)); END PROCEDURE; VARIABLE TX_LOC : LINE; VARIABLE TX_STR : String(1 to 4096); VARIABLE seed1, seed2: positive; VARIABLE i_x, i_y, i_p, i_z, i_yz_modp: integer; VARIABLE cycles, max_cycles, min_cycles, total_cycles: integer := 0; VARIABLE avg_cycles: real; VARIABLE initial_time, final_time: time; VARIABLE xx: std_logic_vector (M-1 DownTo 0) ; BEGIN start <= '0'; reset <= '1'; WAIT FOR PERIOD; reset <= '0'; WAIT FOR PERIOD; for I in 1 to NUMBER_TESTS loop gen_random(xx, M, seed1, seed2); x <= xx; gen_random(xx, M, seed1, seed2); y <= xx; start <= '1'; WAIT FOR PERIOD; start <= '0'; wait until done = '1'; WAIT FOR 2*PERIOD; -- IF ( c(M-2 downto 0) /= z(M-2 downto 0) ) THEN IF ( c /= z ) THEN write(TX_LOC,string'("ERROR!!! C=")); write(TX_LOC, c); write(TX_LOC,string'("/= Z=")); write(TX_LOC, z); write(TX_LOC,string'(" using: ( A =")); write(TX_LOC, x); write(TX_LOC, string'(", B =")); write(TX_LOC, y); write(TX_LOC, string'(", F = 1")); write(TX_LOC, F); write(TX_LOC, string'(" )")); TX_STR(TX_LOC.all'range) := TX_LOC.all; Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; END IF; end loop; WAIT FOR DELAY; ASSERT (FALSE) REPORT "Simulation successful!. Not error detected" SEVERITY FAILURE; END PROCESS; END;