
----------------------------------------------------------------------------
--                            Design Analysis                             --
----------------------------------------------------------------------------
Analyze pcore plb_led7seg ...


----------------------------------------------------------------------------
--                            Design Analysis                             --
----------------------------------------------------------------------------
Analyze pcore plb_led7seg ...


----------------------------------------------------------------------------
--                            File Generation                             --
----------------------------------------------------------------------------
Creating HDL source directory ...
Generating top peripheral VHDL template ...
Generating stub user logic VHDL template ...
HDL templates successfully generated ...
Creating data directory ...
Generating XPS inteface files ...
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_0
0_a/hdl/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_sin
gle_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" in Library
plbv46_slave_single_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_sin
gle_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library
plbv46_slave_single_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Tecno/Xilinx/13.1/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_sin
gle_v1_01_a/hdl/vhdl/plbv46_slave_single.vhd" in Library
plbv46_slave_single_v1_01_a.
Entity <plbv46_slave_single> compiled.
Entity <plbv46_slave_single> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/User/Doctor/papers/libro_Deschamps/edk13.1/led7seg_ip/pcores/plb_led7seg_v1_
00_a/data/../hdl/vhdl/user_logic.vhd" in Library plb_led7seg_v1_00_a.
Entity <user_logic> compiled.
Entity <user_logic> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/User/Doctor/papers/libro_Deschamps/edk13.1/led7seg_ip/pcores/plb_led7seg_v1_
00_a/data/../hdl/vhdl/plb_led7seg.vhd" in Library plb_led7seg_v1_00_a.
Entity <plb_led7seg> compiled.
Entity <plb_led7seg> (Architecture <IMP>) compiled.


Analyzing HDL attributes ...
Entity name = plb_led7seg
INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
INFO:EDK:1486 - HDL set to value : VHDL
WARNING:EDK:3588 - Unable to delete temporary XST project file
   C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip\pcores\plb_led7seg_v
   1_00_a\data\_plb_led7seg_xst.prj : 13
XPS interface files successfully generated ...
Creating development directory ...
Generating command option file ...
Generating readme file ...
Development misc files successfully generated ...
No ProjNavigator support files will be generated at this time ...
No XST synthesis support files will be generated at this time ...
No BFM simulation files will be generated at this time ...
Creating software driver data directory ...
Generating software driver XPS interface (mdd/tcl) files ...
Software driver data definition file (.mdd) successfully generated ...
Software driver data generation file (.tcl) successfully generated ...
Creating software driver src directory ...
Generating software driver template files ...
Software driver compile file (Makefile) successfully generated ...
output user slave register(s) offset to software driver header ...
Software driver header file (.h) successfully generated ...
Software driver source file (.c) successfully generated ...
Software driver SelfTest file (.c) successfully generated ...
Software driver template files successfully generated ...

----------------------------------------------------------------------------
--                              Final Report                              --
----------------------------------------------------------------------------
Thank you for using Create and Import Peripheral Wizard! Please find your
peripheral hardware templates under
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/pcores/plb_led7seg_v1_0
0_a and peripheral software templates under
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/drivers/plb_led7seg_v1_
00_a respectively.

Peripheral Summary:

  top name       : plb_led7seg
  version        : 1.00.a
  type           : PLB (v4.6) slave
  features       : slave attachment

Address Block Summary:

  user logic slv : C_BASEADDR + 0x00000000
                 : C_BASEADDR + 0x000000FF

File Summary

  - HDL source -
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/pcores/plb_led7seg_v1_0
0_a/hdl
  top entity     : vhdl/plb_led7seg.vhd
  user logic     : vhdl/user_logic.vhd

  - XPS interface -
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/pcores/plb_led7seg_v1_0
0_a/data
  mpd            : plb_led7seg_v2_1_0.mpd
  pao            : plb_led7seg_v2_1_0.pao

  - Misc file -
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/pcores/plb_led7seg_v1_0
0_a/devl
  help           : README.txt
  option         : ipwiz.opt
  log            : ipwiz.log

  - Driver source -
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/drivers/plb_led7seg_v1_
00_a/src
  makefile       : Makefile
  header         : plb_led7seg.h
  source         : plb_led7seg.c
  selftest       : plb_led7seg_selftest.c

  - Driver interface -
C:\User\Doctor\papers\libro_Deschamps\edk13.1\led7seg_ip/drivers/plb_led7seg_v1_
00_a/data
  mdd            : plb_led7seg_v2_1_0.mdd
  tcl            : plb_led7seg_v2_1_0.tcl


