
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 13.1 EDK_O.40d
* DO NOT EDIT.
*
* Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xbram.h"

/*
* The configuration table for devices
*/

XBram_Config XBram_ConfigTable[] =
{
	{
		XPAR_DLMB_CNTLR_DEVICE_ID,
		XPAR_DLMB_CNTLR_DATA_WIDTH,
		XPAR_DLMB_CNTLR_ECC,
		XPAR_DLMB_CNTLR_FAULT_INJECT,
		XPAR_DLMB_CNTLR_CE_FAILING_REGISTERS,
		XPAR_DLMB_CNTLR_UE_FAILING_REGISTERS,
		XPAR_DLMB_CNTLR_ECC_STATUS_REGISTERS,
		XPAR_DLMB_CNTLR_CE_COUNTER_WIDTH,
		XPAR_DLMB_CNTLR_ECC_ONOFF_REGISTER,
		XPAR_DLMB_CNTLR_ECC_ONOFF_RESET_VALUE,
		XPAR_DLMB_CNTLR_WRITE_ACCESS,
		XPAR_DLMB_CNTLR_BASEADDR,
		XPAR_DLMB_CNTLR_HIGHADDR
	},
	{
		XPAR_ILMB_CNTLR_DEVICE_ID,
		XPAR_ILMB_CNTLR_DATA_WIDTH,
		XPAR_ILMB_CNTLR_ECC,
		XPAR_ILMB_CNTLR_FAULT_INJECT,
		XPAR_ILMB_CNTLR_CE_FAILING_REGISTERS,
		XPAR_ILMB_CNTLR_UE_FAILING_REGISTERS,
		XPAR_ILMB_CNTLR_ECC_STATUS_REGISTERS,
		XPAR_ILMB_CNTLR_CE_COUNTER_WIDTH,
		XPAR_ILMB_CNTLR_ECC_ONOFF_REGISTER,
		XPAR_ILMB_CNTLR_ECC_ONOFF_RESET_VALUE,
		XPAR_ILMB_CNTLR_WRITE_ACCESS,
		XPAR_ILMB_CNTLR_BASEADDR,
		XPAR_ILMB_CNTLR_HIGHADDR
	}
};


