Synthesis of Arithmetic Circuits:

FPGAs, ASICs and Embedded Systems

 

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Chapter 1: Introduction

Example of section 1.7

 

Chapter 10: Circuit synthesis: general principles

All examples of chapter 10

Example 10.1 (combinational circuit)

Example 10.2 (sequential circuit)

Example 10.4 (long operand)

Example 10.6 (self-timed)

 

Chapter 11: Adders and subtractors

All examples of chapter 11

Example 11.2 (n-digit base-B carry-chain adder)

Example 11.3 (n-digit base-B carry-skip adder)

Example 11.5 (n-digit base-B carry-select adder)

Example 11.7 (two-level n-digit base-B carry-lookahead adder)

Example 11.9 (s**2-digit carry-lookahead adder)

Example 11.10 (n-digit Brent-Kung base-B prefix adder)

Example 11.11 (m-operand n-digit adder)

Example 11.12 (m-operand n-digit sequential carry-save adder)

Example 11.14 (an adder substractor)

Example 11.16 (B's complement adder-subtractor)

Example 11.17 (excess-E adder and subtractor)

Example 11.17bis (excess-E adder and subtractor)

Example 11.18 (sign-magnitude adder)

 

Chapter 12: Adders and Multipliers

All examples of chapter 12

Example 12.1 (n-digit by m-digit base-B basic multiplier)

Example 12.2 (n-bit by m-bit base-2 basic multiplier)

Example 12.3 (n-digit by m-digit base-B basic sequential multiplier)

Example 12.4 (n-bit by m-bit base-2 ripple-carry multiplier)

Example 12.5 (n-bit by m-bit base-2 carry-save multiplier)

Example 12.6 (n-bit by m-bit base-2 ripple carry multiplier using 4 by 2 digits multiplier cell)

Example 12.7 (n-bit by m-bit sequential multiplier for signed operands)

Example 12.12 (n-bit by m-bit booth-1 multiplier for signed operands)

Example 12.13 (n-bit by m-bit booth-2 multiplier for signed operands)

Example 12.14 (n-bit by m-bit booth-3 multiplier for signed operands)

 

Chapter 13: Dividers

All examples of chapter 13

Example 13.1 (n-bits base-2 restoring divider with p-bits quotient and n-bits remainder)

Example 13.2 (n-bits by m-bits base-2 restoring divider with natural quotient of n-bits, and m-bits remainder)

Example 13.3 (Base-B n-digits divider with p-digits quotient and n-digits remainder)

Example 13.4 (n-bits base-2 non-restoring divider with p-bits quotient and n-bits remainder)

Example 13.4bis (n-bits by m-bits base-2 non-restoring divider with quotient of n-bits, and m-bits remainder. There are 3 designs: X and Y naturals, X and Y integers, and integer X and natural Y in this last case the remainder R has one bit more (m+1 bits)).

Example 13.6 (non-restoring Base-B n-digits divider with p-digits quotient and n-digits remainder)

Example 13.7 (n-bits base-2 SRT divider with p-bits quotient and n-bits remainder, 2ís complement remainder)

Example 13.8 (n-bits base-2 SRT divider with p-bits quotient and n-bits remainder. The remainder in carry save format)

Example 13.9 (n-bits base-4 SRT divider with p-bits quotient and n-bits remainder. The remainder is in 2ís complement)

Example 13.10 (n-bits base-2 Newton-Raphson inverter with p-bits quotient)

Example 13.11 (n-bits base-2 goldschmidt divider with p-bits quotient).

 

Extra examples of Chapter 13

div_nr_f_pipe.zip A pipelined version of a n-bits base-2 non restoring divider with p-bits quotient and n-bits remainder. Normalized positive number are required. The constant Depth controls the logic depht.

div_nr_sec.zip A sequential version of a base-2 non restoring divider. For naturals of X and Y-bits. The constant GRAIN defines the amount of bits computed at each cycle. The algorithm needs XBITS/GRAIN + 1 cycles to calculate the result.

 

Chapter 15: Circuits for finite field operations

All examples of chapter 15

Example 15.1 (binary (B = 2) modulo m adders and subtractors)

Example 15.2 (binary (B = 2) modulo m shift-and-add multiplier)

Example 15.3 (binary Montgomery multiplier)

Example 15.4 (computes x modulo 2n - c, x being a 2.n-bit number)

Example 15.5 (a mod 239 reduction circuit)

Example 15.6 (computes y.x modulo m, where x and y are two n-bit numbers)

 

Chapter 16: Floating-point unit

All examples of chapter 16

Example 16.7 (generic floating-point adder-subtractor. It is made up of four blocks)

Example 16.8 (generic floating-point multiplier. It is made up of four blocks)

Example 16.9 (generic floating-point divider. It is made up of three blocks)

 

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This site was last updated 11/02/07